Espressif Systems /ESP32-P4 /MIPI_DSI_BRIDGE /INT_CLR

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Interpret as INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UNDERRUN_INT_CLR)UNDERRUN_INT_CLR

Description

dsi_bridge interrupt clear register

Fields

UNDERRUN_INT_CLR

write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG

Links

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